#ifndef FPGA_MANAGE_H
#define FPGA_MANAGE_H

#include "../global/ObasicTypes.h"
#include "global.h"
#include "fpga_drv.h"
#include "../utils/utils.h"
#include "linux/input.h"
#include "messageDeal/message_deal.h"



#include <vector>
#include <map>
#include <pthread.h>


#define ScreenOn                        1
#define ScreenOff                       0

#define OUT_PORT_NUM                    16//



#define VMF_SEND_DELAY            50    //500ms
#define SEARCH_ORDER_DELAY        80

typedef enum{OPEN,CLOSE}OPTION;

typedef enum{

    eth_state1 = 0x60,      //bit0~bit1 bit3~bit4 1~4
    eth_state2 = 0x200,     //bit0~bit3 5~8
    eth_state3 = 0x201,     //bit0~bit7 9~16

    ETH0_RCVL = 0x64,    //网口0接收卡个数低位
    ETH0_RCVH = 0x65,    //网口0接收卡个数高位
    ETH1_RCVL = 0x66,    //网口1接收卡个数低位
    ETH1_RCVH = 0x67,    //网口1接收卡个数高位
    ETH0_VMF = 0x68,     //网口0多功能卡个数
    ETH1_VMF = 0x6A,     //网口1多功能卡个数
    ETH2_RCVL = 0x6C,    //网口2接收卡个数低位
    ETH2_RCVH = 0x6D,    //网口2接收卡个数高位
    ETH3_RCVL = 0x6E,    //网口3接收卡个数低位
    ETH3_RCVH = 0x6F,    //网口3接收卡个数高位
    ETH2_VMF = 0x70,     //网口2多功能卡个数
    ETH3_VMF = 0x72,     //网口3多功能卡个数
    ETH4_RCVL = 0x230,   //网口4接收卡个数低位
    ETH4_RCVH = 0x231,   //网口4接收卡个数高位
    ETH4_VMF = 0x232,    //网口4多功能卡个数
    ETH5_RCVL = 0x234,   //网口5接收卡个数低位
    ETH5_RCVH = 0x235,   //网口5接收卡个数高位
    ETH5_VMF = 0x236,    //网口5多功能卡个数
    ETH6_RCVL = 0x238,   //网口6接收卡个数低位
    ETH6_RCVH = 0x239,   //网口6接收卡个数高位
    ETH6_VMF = 0x23A,    //网口6多功能卡个数
    ETH7_RCVL = 0x23C,   //网口7接收卡个数低位
    ETH7_RCVH = 0x23D,   //网口7接收卡个数高位
    ETH7_VMF = 0x23E,    //网口7多功能卡个数

    ETH8_RCVL = 0x280,   //网口9接收卡个数低位
    ETH8_RCVH = 0x281,   //网口9接收卡个数高位
    ETH8_VMF = 0x282,    //网口9多功能卡个数
    ETH9_RCVL = 0x284,   //网口10接收卡个数低位
    ETH9_RCVH = 0x285,   //网口10接收卡个数高位
    ETH9_VMF = 0x286,    //网口10多功能卡个数
    ETH10_RCVL = 0x288,  //网口11接收卡个数低位
    ETH10_RCVH = 0x289,  //网口11接收卡个数高位
    ETH10_VMF = 0x28A,   //网口11多功能卡个数
    ETH11_RCVL = 0x28C,  //网口12接收卡个数低位
    ETH11_RCVH = 0x28D,  //网口12接收卡个数高位
    ETH11_VMF = 0x28E,   //网口12多功能卡个数
    ETH12_RCVL = 0x290,  //网口13接收卡个数低位
    ETH12_RCVH = 0x291,  //网口13接收卡个数高位
    ETH12_VMF = 0x292,   //网口13多功能卡个数
    ETH13_RCVL = 0x294,  //网口14接收卡个数低位
    ETH13_RCVH = 0x295,  //网口14接收卡个数高位
    ETH13_VMF = 0x296,   //网口14多功能卡个数
    ETH14_RCVL = 0x298,  //网口15接收卡个数低位
    ETH14_RCVH = 0x299,  //网口15接收卡个数高位
    ETH14_VMF = 0x29A,   //网口15多功能卡个数
    ETH15_RCVL = 0x29C,  //网口16接收卡个数低位
    ETH15_RCVH = 0x29D,  //网口16接收卡个数高位
    ETH15_VMF = 0x29E,   //网口16多功能卡个数


    SP_P1_VMF_ADDR = 0x4000,	//网口1多功能卡地址
    SP_P2_VMF_ADDR = 0x5000,	//网口2多功能卡地址
    SP_P3_VMF_ADDR = 0x6000,	//网口3多功能卡地址
    SP_P4_VMF_ADDR = 0x7000	    //网口4多功能卡地址

} OVP_FPGA_ETH_PRAR_ADDR ;



enum SCREEN_status{SCREEN_BLACK,SCREEN_LIGHT,SCREEN_LOCK,SCREEN_UNLOCK,ENABLE_LCD,DISENABLE_LCD,DSP_RESET_ING,/*DSP_RESET_OK,
                                   DSP_RESET_OK_1,DSP_RESET_OK_2,DSP_RESET_ING_1,*/VBYONE_NO_DIV_MODE,VBYONE_SPLICE_MODE,VBY_DECODE_STATUS,
                   CHECK_FPGA_PHY_RESET,CHECK_FPGA_PHY_OK,
                   VBYONE_IP_RESET_ING,VBYONE_IP_RESET_OK,
                   VBYONE_HPD_RESET,VBYONE_HPD_OK};

typedef struct
{
    unsigned int VerChk_Version;
    unsigned long long addr;
    unsigned int size;
    unsigned int VerChk_Size;
} __attribute__((__packed__)) MSYS_MMIO_INFO;


typedef enum {
    GPIO14_CONTENT_H = 0x0010,
    GPIO14_CONTENT_L = 0x0000,

    GPIO85_CONTENT_H = 0x0010,
    GPIO85_CONTENT_L = 0x0000,

    GPIO4_CONTENT_H = 0x0010,
    GPIO4_CONTENT_L = 0x0000,

    FPGA2_FPGA_CMD_CONTENT_H = 0x0010,
    FPGA2_FPGA_CMD_CONTENT_L = 0x0000,

    GPIO88_CONTENT_H = 0x0010,
    GPIO88_CONTENT_L = 0x0000,

    GPIO47_CONTENT_H = 0x0010,
    GPIO47_CONTENT_L = 0x0000,

    GPIO48_CONTENT_H = 0x0010,
    GPIO48_CONTENT_L = 0x0000,


    GPIO17_CONTENT_H = 0x0010,
    GPIO17_CONTENT_L = 0x0000,

    GPIO71_CONTENT_H = 0x0001,
    GPIO71_CONTENT_L = 0x0000,

    GPIO53_CONTENT_H = 0x0010,
    GPIO53_CONTENT_L = 0x0000,

    GPIO54_CONTENT_H = 0x0010,
    GPIO54_CONTENT_L = 0x0000,

    GPIO55_CONTENT_H = 0x0010,
    GPIO55_CONTENT_L = 0x0000,

    GPIO58_CONTENT_H = 0x0010,
    GPIO58_CONTENT_L = 0x0000,

    GPIO0_CONTENT_H = 0x0010,
    GPIO0_CONTENT_L = 0x0000,

} OVP_GPIO_REG_VALUE;


typedef enum{

    TIMEOUT_DELAY = 6000
} OVP_CARD_LOCK;


typedef enum{
    FPGA_VBO_INIT_START,
    FPGA_VBO_INIT_S1,
    FPGA_VBO_INIT_S2,
    FPGA_VBO_INIT_S3,
    FPGA_VBO_INIT_S4,
    FPGA_VBO_INIT_S5,
    FPGA_VBO_INIT_S6,
    FPGA_VBO_INIT_S7,

    FPGA_VBO_INIT_END

} OVP_FPGA_VBO_INIT_SETUP;


typedef enum{
    FPGA_PHY_INIT_START,
    FPGA_PHY_INIT_S1,
    FPGA_PHY_INIT_S2,
    FPGA_PHY_INIT_S3,
    FPGA_PHY_INIT_S4,
    FPGA_PHY_INIT_S5,
    FPGA_PHY_INIT_S6,
    FPGA_PHY_INIT_S9,
    FPGA_PHY_INIT_S200,
    FPGA_PHY_INIT_S300,
    FPGA_PHY_INIT_S400,
    FPGA_PHY_INIT_S500,
    FPGA_PHY_INIT_S501,
    FPGA_PHY_INIT_S502,
    FPGA_PHY_INIT_S600,
    FPGA_PHY_INIT_S601,
    FPGA_PHY_INIT_S602,
    FFPA_PHY_INIT_WAIT,

    FPGA_PHY_INIT_END

} OVP_CHECK_FPGA_PHY_INIT_SETUP;


typedef struct{
    Ouint8 type;                // 1:smart mapping  2:load scan  3.save para
    Ouint8 state;
    Ouint8 port;
    Ouint8 package;
    Ouint8 sequence;
    Ouint8 step;
    Ouint8 rcv_back;
    Ouint16 card_index;
    Ouint16 card_num;
    Ouint16 send_len;
    Ouint32 offset;
    Ouint32 timeticks;
    Ouint8 screen_index;
    Ouint8 net_index;
    Ouint8 rcv_index;
    Ouint8 operate_index;
    Ouint8 operate_status;
    Ouint16 rcv_back_info;
    Ouint8 operate_timout;

}Rcv_Card_Send_Para;

typedef enum{
    SMART_PARA_INIT,
    //快捷点屏
    LED_ON_QUICK,
    //加载扫描
    LOAD_SCAN_PARA,
    //参数固化
    SAVE_RCV_PARA_TO_FLASH,
    //mapping
    MAPPING_ENABLE,
    //rcv_recovery check
    RCV_RECOVERY_CHECK,
    //rcv_recover_self_recovery
    RCV_RECOVERY_SELF,

} OVP_SMART_LED_PARA;

typedef struct{
    Ouint16 ConfigRcvTimes ;
    Ouint8 FileVer;

}RcvBxfile;


typedef enum{
    FPGA_VER_START_YEAR = 0x19,
    FPGA_VER_END_YEAR = 0x30,

} OVP_FPGA_START_END_YEAR;


typedef enum{
    TO_RCV_BIND_RESULT_WAIT = 0,
    TO_RCV_BIND_RESULT_NEXT = 1,
    TO_RCV_BIND_RESULT_BACK = 2,
    TO_RCV_BIND_RESULT_OVER = 9,

    TO_RCV_BIND_STATUS_START = 2,
    TO_RCV_BIND_STATUS_WAIT = 3,
    TO_RCV_BIND_STATUS_SEND_HALF1 = 4,
    TO_RCV_BIND_STATUS_SEND_HALF2 = 6,
    TO_RCV_BIND_STATUS_WAITHFALF1_RESUT = 5,
    TO_RCV_BIND_STATUS_WAITHFALF2_RESUT = 7,

    TO_RCV_BIND_STATUS_END

} OVP_RCV_BIND_INFO;


class fpga_manage
{
public:
    fpga_manage() ;
    ~fpga_manage() ;

    Oint8 initialize();
    static fpga_manage* pInstance() ;

    void read_fpga_register(Ouint32 reg, Ouint8 *value,Ouint8 sel_fpag) ;
    void write_fpga_register(Ouint32 reg, Ouint8 value, Ouint8 sel_fpag, Ouint8 reg_mask) ;
    void write_LCD_register(Ouint32 reg, Ouint8 *value, Ouint8 sel_fpag ,Ouint8 num_len );
    Ouint32 fpga_cmd_to_spi_data(Ouint32 ram_flash_sel, Ouint32 ram_addr,Ouint32 start_addr, Ouint32 wr_rd) ;
    Ouint32 fpga_reg_cmd_to_spi_data(Ouint32 ram_flash_sel, Ouint32 ram_addr,Ouint32 start_addr, Ouint32 wr_rd, Ouint32 data) ;

    void read_from_register(Ouint8 reg_addr,Ouint8 sel_fpag) ;
    void write_to_register(Ouint8 reg_addr,Ouint8 reg_mask,Ouint8 reg_data,Ouint8 sel_fpag) ;
    Oint8 setMmapHig(Oint8* addr, Ouint32 value);
    Oint8 setMmapLow(Oint8* addr, Ouint32 value);
    Oint8 setGpioInOutPut(Ouint8 block, Ouint8 number, Obool value);
    Oint8 setGpioHigLow(Ouint8 block, Ouint8 number, int value);
    Oint8* getMmapAddr(Ouint8 block);
    Oint8 getGpioReadStatus(Ouint8 block, Ouint8 number);


    int flash_sel1_setlevel(int num);
    int fpga_program1_setlevel(int num);
    int mcu_ctla_cmd1_setlevel(int num);
    Ouint8 fpga_ctl_int1_gpio_get(void);


public:
    static void write_fpga_ram(Ouint8* buf,Ouint32 addr,Ouint32 len,Ouint8 ram_num,Ouint8 sel_fpag) ;
    static void read_fpga_ram(Ouint8* buf,Ouint32 addr,Ouint32 len,Ouint8 ram_num,Ouint8 sel_fpag) ;
    void get_control_uid(/*int fd ,*/Ouint8 sel_fpag) ;
    void record_check_time(void) ;
    void record_bright_change(void);
    void record_onoff_time(/*int fd ,*/Ouint8 sel_fpag) ;
    void fpga_flash_access() ;
    Ouint8 get_eth_param_addr(Ouint8 eth_num,Ouint16* addrx,Ouint16* addry,Ouint16* addrw,Ouint16* addrh);
    Ouint8 get_eth_min_x_y(Ouint8 sel_fpag,Ouint16* min_x,Ouint16* min_y);
    Ouint8 get_eth_max_border(Ouint8 sel_fpag,Ouint16* max_w,Ouint16* max_h);
    Ouint8 get_eth_lcd_x_y(Ouint8 sel_fpag,Ouint16* lcd_x,Ouint16* lcd_y);
    Ouint8 get_eth_lcd_w_h(Ouint8 sel_fpag,Ouint16* lcd_w,Ouint16* lcd_h);
    void eth_param_init(Ouint8 flag,Ouint8 sel_fpag) ;
    bool check_fpga_ram_param(Ouint8 sel_fpag);
    void update_eth_state(Ouint8 sel_fpag) ;
    void FPGA_to_RAM(Ouint8 sel_fpag) ;
    void fpgainit(Ouint8 sel_fpag) ;
    void G32_mcu_set_net_para(Ouint8 sel_fpag) ;
    void G32_back_mcu_set_net_para(Ouint8 sel_fpag) ;
    void G32_mcu_set_lcd_x_y_para(Ouint8 sel_fpag);
    void Brightness_init(Ouint8 *data);

    Ouint32 get_wlan_state();
    void check_wlanonline_state();
    void SCREEN_fpgactrl_status(enum SCREEN_status status);
    void SCREEN_fpgactrl_status2(enum SCREEN_status status,Ouint8 sel_fpag);

    void set_lcd_change_flag(void);
    void set_9022_para(int i);

    Ouint16 get_port_card_num(Ouint8 port_num);
    void get_rcvcard_x_y(int index ,Ouint16 *card_x, Ouint16 *card_y);
    void rcv_card_cmd_create(Ouint8* send_buf, Ouint8 port_num);
    void SmartMapping_deal(void);
    //Ouint8 load_file_analysis(const char* name,Ouint8* buf,uint16 length);
    //void load_scan_cmd_create(Ouint8* send_buf,SCAN_PARA *scan_para);
    void load_write_ram_cmd_create(Ouint8 port,Ouint8 card_index,Ouint32 ram_addr, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf, bool smart_net);
    void save_para_cmd_create(Ouint8* send_buf, Ouint8 port_num);
    Ouint16 load_write_reg_cmd_create(Ouint8 port,Ouint8 card_index, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf,bool smart_net);
    Ouint16 load_write_user_defined_cmd_create(Ouint8 port,Ouint8 card_index, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf,bool smart_net);
    Ouint16 load_search_rxc_cmd_create(Ouint8 port, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf);


    Ouint16 save_para2flash_cmd_create(Ouint8 port,Ouint8 card_index, Ouint8 *send_buf, bool smart_net);
    Ouint16 rcv_active_firmware_cmd_create(Ouint8 port,Ouint8 card_index,Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf);
    Ouint16 rcv_reconfig_cmd_create(Ouint8 port,Ouint8 card_index,Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf/*,bool smart_net*/);
    void mapping_enable_cmd_create(Ouint8 port,Ouint8 *send_buf);
    void ram_reset_cmd_create(Ouint8* send_buf,SCAN_PARA *scan_para, Ouint8 port_num);
    Ouint8 get_operate_deal_para(SCAN_PARA *scan_para,Ouint8 index);
    Ouint8 load_rcv_xy_operate(string files_rcv, Ouint32 offset,  bool smart_net);
    void save_para_deal(void);
    void mapping_enable_deal(void);

private:
    //static void * check_fpga_irqEventThread(void * p_about_fpga_manage);
    static void * fpgamanageThread(void * p_about_fpga_manage);
    static void fpga_manage_deal(void * p_about_fpga_manage) ;
    static void usb_upgrade_manage_deal(void * p_about_fpga_manage) ;
    static void * timeThread(void *arg);
    pthread_t m_pidfpgamanage;


public:
    pthread_mutex_t m_fpga_reg;
    pthread_mutex_t m_fpga_manage;
    //pthread_mutex_t m_fpga_passby_trans;
    //    pthread_mutex_t m_fpga_gpio_echo_init_mutex;

public:
    static fpga_manage *p_fpga_manage ;
    //    Ouint8 fpga_gpio_echo_init;

    Ouint8 data_from_eth[FRAME_DATA_LEN];
    Ouint16 data_from_eth_len;

    Ouint8  g_sync_netport_trans_mode;
    Ouint32 g_netport_trans_ticks;
    Ouint32 g_fpga_ack_statue;
    Ouint8  g_check_netport_trans_mode=0 ;//!<用于检查并发模式  并发的超时时间为5秒左右
    Ouint8  g_net_frame_seq;              //!<用于标记当前帧序号
    Ouint8  g_dataflow_flag;              //!<用于标记当前是否为data flow模式

    Ouint32 g_lcd_change[2];
    Ouint32 g_lcd_ret_time[2];
    Ouint32 g_lcd_delay_time[2];//OVP_CONTROL_OUT_NUM
    bool check_fpga_ram_status[2];

    //    bool l_check_time_update = false;
    bool fpga1_rst_flag = false;
    bool fpga2_rst_flag = false;
    Ouint32 fpga1_rst_ticks ;
    Ouint32 fpga2_rst_ticks ;
    Ouint8  Timeout_flag;
    Ouint8  rcv_locksend_over;
    Ouint8  rcv_unlocksend_over;
    Ouint8  to_rcv_sure_cmd_num;
    Ouint8  to_rcv_sure_status;
    Ouint8  to_rcv_sure_error;
    Ouint8  to_rcv_sure_checktimes;
    Ouint32 to_rcv_sure_cmd_39;
    Ouint8  output_status;//black light freeze
    Ouint8 VMF_port_data_valid;
    Ouint8 G_VMF_VALUE_back[0x80+2];

    bool set_fpga_lcd_para = false;
    bool set_fpga_bri_para = false;
    Ouint32 set_led_para_ticks = 0;
    Ouint32 set_led_check_times = 0;
    //Ouint8 net_wati_send_flag[2][DEVICE_OUT_NUM/2] = {0};

    bool set_fpga_multicast_mode=false;//false  brodcast   true multicast
    Ouint32 fpga_multicast_net=0;//set_fpga_multicast_mode true valid
    Ouint8 passby_trans_port_over;

    Ouint8 rcv_screen_index;
    Ouint8 rcv_net_index;
    Ouint8 rcv_self_index;
    Ouint8  flash_uid[16];
    Ouint32 device_id;
    vector<string> firmware_list_path;
    Ouint32 usb_updata_list;
    Ouint8 downing_mcu;
    Ouint8 downing_txc1;
    Ouint8 downing_txc2;
    Ouint8 downing_osd;
public:
    fpga_drv *p_fpga_drv ;
    //    int fpga1_irq_fd;
    //    int fpga2_irq_fd;





public:
    int fpga_vbyone1_fd ;
    int fpga_vbyone2_fd ;
    int fpga_vbyone1_flash_fd;
    int fpga_vbyone2_flash_fd;

private:

    bool _runFlag;		// 相当于g_xsercmdflag ,设置屏参停止设置亮度与获取传感器值
    time_t _timeStamp;

    int fpga_irq_vbyone_event_fd ;
    fd_set m_fpga_irq_fdReads;


    Ouint8  MCU_REG_VBYONE1[REG_MAX_NUM]={0};	        //!<寄存器区数据保存数组

    Ouint8   MCU_RAM_PARA_VBYONE1[FPGA_RAM_MAX_LEN];       //!<FPGA 与 MCU 共同的参数 RAM 地址

    Ouint8   MCU_RAM_RX_VBYONE1[FPGA_RAM_MAX_LEN];         //!<FPGA 接收网口数据的缓存区

    Ouint8   MCU_RAM_TX_VBYONE1[FPGA_RAM_MAX_LEN];         //!<FPGA 发送网口数据的缓存区


    Ouint8   MCU_RAM_ETH_VBYONE1[MCU_RAM_ETH_LEN];         //JUST FOR C331

    Ouint8   MCU_RAM_ETH_BACK_VBYONE1[MCU_RAM_ETH_LEN];    //JUST FOR C331

    TimeRealType check_time;
    TimeRealType start_time;
    Ouint32 g_netport_recored ;    //!<用来标记本次是否有网口发送  1表示 1/3/5/7  2表示2/4/6/8 0无网口发送
    Ouint32 g_netport_recored1;
    Ouint32 g_netport_to_rcv_sure_recored;
    Ouint32 g_BrightnessMode ;
    Ouint32 g_Bri_table_change;
    //    Ouint8 g_fpga_irq_event_value ;
    //Ouint8 net_wati_send_flag[DEVICE_OUT_NUM];

    //    uint32 check_fpga_irq_ticks;
    Ouint32 g_timeout_ticks = 0;
    bool  search_card_flag = false;
    bool  wait_new_time = false;
    Ouint8 GroupNum;
    Ouint8 on_off_status;
    Ouint8 check_date;

    Ouint8  OnHour[8];
    Ouint8  OnMinute[8];
    Ouint8  OffHour[8];
    Ouint8  OffMinute[8];
    Ouint8  on_flag[8];
    Ouint8  off_flag[8];
    //Ouint8  timeout_buf[75];

    Ouint8 G_VMF_VALUE[0x80];

public:
    TimeRealType read_time;
    bool  new_check_time = false;
    Ouint8  timeout_buf[102];
    Ouint16 wlan_state_old[2]={0};
public:
    RcvBxfile g_load_scan_para ;


private:
    //about fpga init
    void softinit();
    void Version_to_RAM(void);
    void PHY_status_to_RAM(void);
    void power_up_fpga_start(Ouint8 flag,Ouint8 sel_fpag) ; //!< check the fpga
    void power_up_check_fpga_status(Ouint8 sel_fpag);
    //void check_fpga_singal_reset(Ouint8 sel_fpga);
    void reset_fpga_rst(Ouint8 sel_fpga);
    void check_fpga_rst(void);
    void Record_Time_Deal(void) ;
    Ouint8 check_TimeOut_cmp(TimeRealType *ps_time,TimeRealType *rtc_time) ;
    Ouint8 Check_TimeOut(void) ;
    void Check_search_card(void);
    Ouint8 set_output_status(void);
    Ouint8 set_fpga_lcd(void);
    Ouint8 set_fpga_bri_val(void);
    void set_led_para_deal(void);
    //    Ouint8 get_fpga_status(void) ;
    void Search_Card_Cmd(void) ;
    Ouint8 check_vbo_status(Ouint8 sel_fpag);
    void CHECK_search_cmd_status(void) ;
    Ouint8 to_rcv_sure_send(Ouint8 status ,Ouint32 len, Ouint8 *data);
    void Send_rcv_card_cmd(Ouint32 port_num,Ouint8 type,Ouint8 sel_fpag) ;
    void check_error_rcv_search_card_cmd(Ouint32 port_num,Ouint8 sel_fpag,Ouint32 screen_id, Ouint32 config_id, Ouint8 config_id_enable);
    void Send_to_port(Ouint8* eth_cach,Ouint16 data_len,Ouint16 port_num,Ouint8 sel_fpag) ;
    void Extension_function(void) ;
    void Brightness_task(void) ;
    void dealwith_onoff(void);
    void Brightness_hand_change(void);
    void Brightness_time_change(void);
    void Brightness_auto_change(void);
    void Brightness_check_VMF(void);
    void Brightness_read_VMF_value(void);
    void Send_read_VMF_data_cmd(void);
    void Brightness_VMF_run(void);
    void VMF_data_back_result(void);
    void Brightness_auto_filter(void);
    //    void reg_IRQ_Dealwith(Ouint8 sel_fpag) ;
    //    int check_fpga_irq(Ouint8 sel_fpag) ;
    void Rcv_data_from_eth(Ouint8 sel_fpag);

    Ouint32 check_netport_card(void);
    bool wait_fpga_send_ready(Ouint8 port_num,Ouint8 sel_fpga);
    void rxc_lock_cmd_create(Ouint8 port_num,Ouint8* SEND_RXC_LOCK_CMD);
    void rxc_lock_cmd_create1(Ouint8* SEND_RXC_LOCK_CMD);
    void rxc_unlock_cmd_create(Ouint8 port_num,Ouint8* SEND_RXC_LOCK_CMD);
    void rxc_unlock_cmd_create1(Ouint8* SEND_RXC_LOCK_CMD);
    void rxc_unbind_cmd_create(Ouint8 port_num,Ouint8* SEND_RXC_LOCK_CMD,Ouint8 bind);
    void rxc_unbind_cmd_create1(Ouint8* SEND_RXC_LOCK_CMD,Ouint8 bind,Ouint8 sec_type);
    void rxc_lock_set(void);
    void send_rxc_lock_cmd(void);
    void send_rxc_unlock_cmd(void);
    Ouint8 send_device_rcv_bind_cmd(Ouint8 bind, Ouint8 status, Ouint8 sec_type);
    void multi_port_send(Ouint8* data, Ouint16 data_len);
    //void check_fpga_irq_status(Ouint8 sel_fpag);
    void check_fpga_net_data_status(Ouint8 sel_fpag);
    Ouint8 deal_with_search_concurrent(Ouint8 sel_fpag);
    void Search_concurrent_back_result(PhyData_Type *msg,Ouint8 group,Ouint8 sel_fpag,Ouint32 len);
    void update_eth_rcv_num(PhyData_Type *msg,Ouint8 port,Ouint8 sel_fpag);
    void get_usb_file_list_path(void);
    void usb_upgrade_main_deal(void);
    void update_c331_osd_font_file(char *sy_name, Ouint32 file_offset, Ouint32 file_len);
    void update_txc_file(char *sy_name, Ouint8 flashName, Ouint32 file_offset);
    void update_muc_file(char *sy_name, Ouint32 file_offset, Ouint32 file_len);

public:
    Ouint8 IT8563WE_Get(TimeRealType* now);
public:
    void Dealwith_mcu_ram(void);
    void Checktime(void);
    void OnOff_time();
    int Brightness_hand_dealwith(Ouint8 type);
    int Brightness_message_dealwith(Ouint8 value);
    
    //    void Brightness_save_rcv(void);
    //    Ouint8 judge_card_state(uint32 port,uint32 *port1);
    void Search_Card_task_run(void);
    void Brightness_task_run(void);

    void Power_ctrl_init(void);
    void Power_ctrl_reset(void);
    void Power_ctrl_deal(void);
    void eth_data_send_stop(void);
    void eth_data_send_start(void);
    void Send_write_VMF_reg_cmd(OPTION option,Ouint8 io_num);
    void wait_VMF_result(void);
    void VMF_reg_back_result(Ouint8 sel_fpga);
    void Power_ctrl_task(void);
    void Power_check_VMF(void);
    void Power_read_VMF_value(void);
    void Power_ctrl_filter(void);
    void Send_read_VMF_RAM0_data_cmd(void);
    void Power_VMF_run(void);
    void VMF_RAM0_data_back_result(Ouint8 sel_fpga);
    string checkVersion();
    bool getRunFlag(){ return _runFlag; }
    void setRunFlag(bool status){ _runFlag = status; }
    time_t getTimeStamp(){ return _timeStamp; }
    void updateTimeStamp(){ _timeStamp = time(0); }


public:
    Ouint8 Dealwith1_PC_to_eth(Ouint32 len, Ouint8 *data);
    void reg_IRQ_Dealwith(Ouint8 sel_fpag, Ouint8 mode) ;
    Ouint8 get_fpga_status(void) ;

public:
    static Ouint8 *MCU_REG_func[1];
    static Ouint8 *MCU_RAM_PARA_func[1];
    static Ouint8 *MCU_RAM_RX_func[1] ;
    static Ouint8 *MCU_RAM_TX_func[1] ;
    static Ouint8 MCU_RAM_DEFAULT[FPGA_RAM_DEFAULT_LEN] ;
    static Ouint8 MCU_RAM_ZOOM[FPGA_RAM_MAX_LEN] ;
    static Ouint8 MCU_RAM_CMD[FPGA_RAM_MAX_LEN] ;
    static Ouint8 MCU_RAM_EXTEND[FPGA_RAM_MAX_LEN] ;
    static const Ouint8 RAM1[];
    static Ouint8  SEND_READ_VMF_RAM0_CMD[19];
    static Ouint8  SEARCH_CARD_BUF[15];
    static Ouint8  SEND_BRI_ETH_CMD[20];
    static Ouint8  SEND_BRI_ETH_REG[15];
    static Ouint8  SEND_BRI_SAVE_CMD[13];
    static Ouint8    HalfHourValue[48];
    static Ouint8 *MCU_RAM_ETH_PARA_func[1];//just for G32
    static Ouint8 *MCU_RAM_ETH_BACK_PARA_func[1];//just for G32
    Ouint8 G_VMF_RAM0_VALUE[0x100];
    Ouint8 check_fpga_phy_status[1];
    Ouint8 green_check_ok[1];
    Ouint32 check_fpga_phy_ticks[1];
    Ouint8 fpga_init_step[1];
    Ouint8  check_frame_stable[1] ;
    Ouint8  check_frame_reset[1] ;
    Ouint16 fpga_init_error[1];
    Ouint8 fpga_init_rst_times[1];
    Ouint8 fpga_vbo_status[1];
    Ouint8 fpga_vbo_check_setup[1];
    Ouint16 fpga_vbo_check_times[1];


    Ouint8 g_power_ctrl_flag;
    Ouint8 g_power_ticks_flag;
    Ouint8 g_first_start_flag;
    Ouint8 g_signal_state;
    Ouint8 g_power_open_running;
    Ouint8 g_power_close_running;
    Ouint8 g_power_io_num;
    Ouint8 g_power_port_num;
    Ouint8 g_power_sel_fpga;


    Ouint16 g_dvi_count[1];
    Ouint16 g_vbo_count[1] = {0};
    string str_record_time;

public:
    Oint8 *m_baseGpio0;
    Oint8 *m_baseGpio1;
    Oint8 *m_baseGpio2;
    Oint8 *m_baseGpio3;
    Oint8 *m_baseGpio4;

    int m_memFd;
    int msys_fd ;
    MSYS_MMIO_INFO m_info;

    //unsigned long addr_gpio85;
    //unsigned long addr_gpio4;




    //FPGA FLASH片选信号(由于FPGA也需要控制FLASH)
    //
    // unsigned long to_fpga1_spi_flash_sel;

    //FPGA复位重启控制IO
    //
    unsigned long to_fpga1_reset;

    //FPGA告知有数据需要读取
    //
    unsigned long in_fpga1_irq_event;



};


extern Rcv_Card_Send_Para g_send_para;


#endif














// C331_MANAGE_H
